NPTEL Computer Architecture Week 10 Assignment Answers 2024
1. Which of the following statements is false with respect to the instruction pipeline?
- Pipelining can increase the throughput of a system.
- Pipelining partitions the system into multiple independent stages with added buffers between the stages.
- Pipelining reduces the latency of each individual instruction.
- None of the options.
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2. Which of the following is stored in the pipeline register between the Instruction Fetch and Operand Fetch stages of an instruction pipeline ?
- Only the content of the instruction.
- Only the PC value.
- Both the PC value and the content of the instruction.
- None of the options.
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3. Consider the following two statements regarding the performance of a pipelined processor. Choose the correct option:
[S1] The performance will not suffer if the pipeline stages have different delays.
[S2] The performance will suffer if consecutive instructions are dependent on each other.
- Both S1 and S2 are true.
- Only S2 is true.
- Only S1 is true.
- Both S1 and S2 are false.
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4. How many latches are required in a 7-stage pipelined processor?
- 6
- 4
- 7
- 10
Answer :-
5. Which of the following statements is false with respect to forwarding in a 5-stage pipelined processor ?
- Forwarding cannot prevent all pipeline stalls.
- Forwarding does not require any extra hardware to retrieve the datafrom the pipeline stages.
- Forwarding is a method to transfer values of operands between instructions in different pipeline stages through direct connections between the stages.
- None of the options.
Answer :-
6. Hazards due to resource conflicts are known as:
- Structural Hazards
- Data Hazards
- Control Hazards
- None of the options.
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7. As per the ____________ condition, instructions in the wrong path are never executed.
- Branch lock
- Data lock
- All the instructions are always executed.
- None of the options.
Answer :-
8. _____________ represents the possibility of erroneous execution because of the unavailability of correct data.
- Data Hazard.
- Structural Hazard.
- Control Hazard.
- None of the options.
Answer :-
9. A branch instruction is known as a ___________ if the processor assumes that all the succeeding instructions that are fetched before its outcome has been determined, are on the correct path.
- Delayed branch
- Conditional branch
- Unconditional branch
- None of the options.
Answer :-
10. The following code snippet will have which type of hazard?
add r1, r2, r3
mul r2, r5, r6
- WAW
- WAR
- RAW
- None of the options.
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