NPTEL Computer Architecture Week 6 Assignment Answers 2024

NPTEL Computer Architecture Week 6 Assignment Answers 2024

1. In a PMOS transistor, when a negative gate voltage is applied, the current flows from the ___ to the ____.

• source, drain
• drain, source
• source, gate
• None of the options

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2. In a NAND gate designed using CMOS logic, how are the two NMOS and two PMOS transistors arranged?

• Two NMOS transistors are arranged in parallel, and two PMOS transistors are arranged in series.
• Two NMOS transistors are arranged in series, and two PMOS transistors are arranged in parallel.
• Two NMOS transistors and two PMOS transistors are arranged in series.
• Two NMOS transistors and two PMOS transistors are arranged in parallel.

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3. Which of the following combinations is not allowed in a non-clocked SR latch built with NOR gates?

• S=0, R=0
• S=0, R=1
• S=1, R=0
• S=1, R=1

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4. Given the Boolean function F(A,B) = (A⋅B)’ + (A+B)’ , which of the following statements is true? Here, ‘ stands for the bit complement (NOT operation).

• The function can be implemented using only NAND gates.
• The function is equivalent to A’+B.
• The function is equivalent to A.B.
• None of the options

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5. Choose the false option from the following.

• An SRAM cell contains two cross-coupled inverters.
• An SRAM cell uses one transistor to save a bit.
• A DRAM cell uses a single transistor and a capacitor.
• None of the options

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6. What is the output of a JK flip-flop when both J and K inputs are 0?

• The output toggles.
• The output is set to 1.
• The output is set to 0.
• The output is unchanged.

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7. Which of the following accurately describes the function of a demultiplexer?

• It routes a single input to one of the several outputs based on select lines.
• It combines multiple inputs into a single output.
• It decodes a binary value to select one of the outputs.
• None of the options

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8. If you have a 512X1 multiplexer, how many select lines are required?

• 6
• 9
• 7
• 8

Answer :- 

9. Why is it necessary to periodically refresh DRAM cells?

• To increase the speed of data access in memory.
• To ensure data is not lost as the charge in the capacitors gradually leaks away.
• There is no need to periodically refresh it.
• None of the options.

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10. Which memory technology is generally less dense and has a lower storage capacity?

• SRAM
• DRAM
• Both SRAM and DRAM have similar densities.
• Storage capacity depends on the specific implementation, not the memory type.

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