NPTEL Computer Architecture Week 9 Assignment Answers 2024
1. The last stage of a 5-stage SimpleRISC processor is the ___________.
- Instruction fetch stage
- Operand fetch stage
- Register write stage
- Memory access stage
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2. The data path does not consist of a/the __.
- Register File
- Memory
- ALU
- None of the options
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3. The __ stage of a 5-stage SimpleRISC processor executes a load or store instruction.
- Operand Fetch (OF)
- Execute (EX)
- Memory Access (MA)
- Register Write (RW)
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4. What is the value of the isBranchTaken control signal for the ret instruction? Choose the most appropriate answer.
- 1
- 0
- 1 if the branch is taken (conditional)
- 0 if the branch is not taken (conditional)
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5. The __ path consists of all the elements in a processor that are dedicated to storing, retrieving, and processing data.
- Control
- Data
- Memory
- Register
Answer :-
6. In horizontal microprogramming, the total size of the encoded instruction is __________ bits.
- 65
- 43
- 32
- 40
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7. The ___________ microinstruction makes the μcontrol unit wait for one cycle and populates all the decode registers in this cycle.
- mLoadIR
- mLoad
- mDecode
- mb
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8. ____________ microprogramming requires a decode stage for generating all the control signals.
- Vertical
- Horizontal
- Data
- None of these
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9. The __ control signal decides whether the instruction writes to a register or not.
- isImmediate
- isWb
- isSt
- isLd
Answer :-
10. Which of the following functions are performed by the operand fetch unit of a 5-stage SimpleRISC processor? Choose the most appropriate option.
- Fetch the register operands from the register file
- Generate control signals
- Decode the instruction
- All of the options
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