NPTEL Operating System Fundamentals Week 10 Assignment Answers 2024

1. In a paging system with TLB. It takes 30ns to search the TLB, and 50ns to search for access to the memory. If the TLB hit ratio is 85%, what is the effective memory access time?

(A) 83ns
(B) 87.5ns
(C) 85.5ns
(D) 84ns
(E) 80.5ns

Answer :- For Answers Click Here

2. A computer system with 512 bytes of main memory runs a process with four segments of unequal size. The process is loaded in the main memory using the following segment table.

Segment number	Base Address (in decimal)	Length (in bytes)
0	20	40
1	80	50
2	135	30
3	180	100

If the computer system uses the 11-bit addresses, what is the physical address corresponding to the logical address 11000001101?

(A) 011001001
(B) 011001100
(C) 111001101
(D) 011001101
(E) Address is out of the segment

Answer :- For Answers Click Here

3. Choose the correct statement for the hashed page table.

(A) It is primarily used in systems with small address spaces.
(B) It stores page table entries in a contiguous memory block.
(C) Each hashed table entry stores only the frame number of the corresponding page.
(D) It is generally faster than an inverted page table.
(E) It uses the virtual page number to compute the hash value, which determines the location in the table.

Answer :- For Answers Click Here

4. The physical address in an inverted page table memory management scheme is the combination of

(A) process id and virtual page number
(B) index of the page table and virtual page number
(C) index of the page table and offset
(D) index of the page table and process id
(E) None of these

Answer :-

5. Choose the correct statement for Intel IA-32 architecture.

(A) It supports 64-bit general-purpose registers
(B) It supports 64-bit physical address space
(C) It supports a three-level paging scheme
(D) It supports 4KB or 4MB page sizes
(E) It does not support a paging scheme

Answer :-

6. The Effective Memory Access time for the Demand paging scheme is directly affected by

(A) degree of multi-programming
(B) number of pages
(C) number of frames
(D) size of memory
(E) page fault rate

Answer :- For Answers Click Here

7. Choose the main benefit of using a hierarchical (multi-level) paging scheme over a single-level paging scheme.

(A) It decreases the page fault rate
(B) It reduces memory access overhead
(C) It decreases the page table size
(D) It improves the physical memory utilization
(E) It simplifies the address translation process

Answer :-

8. Choose the correct statement.

(A) The valid bit in the page table entry indicates that the corresponding page is available in the main memory.
(B) The invalid bit in the page table entry means the page is inaccessible and may cause a page fault if referenced.
(C) The valid/invalid bits ensure that a process can only access its address space and not the address space of other processes.
(D) The valid/invalid bits help make page replacement decisions.
(E) All of the above.

Answer :-

9. Assume that a computer system uses an inverted page table for memory management. The system uses a 16-bit virtual address, and each virtual address is of the form . The size of process id, virtual page number, and offset are 4 bits, 6 bits, and 6 bits, respectively. Assume that the system uses the physical address of 9 bits. The page table of the system is given below.

If the CPU generates the virtual address 1010100101101010, what is the corresponding physical address?

(A) 011101010
(B) 110101010
(C) 000101010
(D) 011101111
(E) 011111110

Answer :-

10. Which actions occur when a page fault happens in a demand paging system?

(A) The process is terminated immediately.
(B) The requested page is loaded from secondary storage into physical memory.
(C) The process is suspended until all pages are swapped out.
(D) The page table entry is marked as invalid.
(E) The physical memory is immediately allocated to the process.