NPTEL Operating System Fundamentals Week 9 Assignment Answers 2024
1. Assume that the computer system’s memory includes eight pages, and each page size is 1KB. The size of the physical memory is thirty-two pages. The number of bits required to represent the logical address and physical address are
(A) 13 bits and 15 bits
(B) 12 bits and 16 bits
(C) 14 bits and 14 bits
(D) 11 bits and 17 bits
(E) 16 bits and 12 bits
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2. Choose the correct statement.
(A) Base register holds the starting address of a memory block or segment.
(B) Base register ensures that a program can only access memory locations within its allocated segment.
(C) Base register allows the program to run correctly regardless of its actual location in memory for dynamic memory allocation.
(D) Base register can reduce the need for frequent memory address recalculations.
(E) All of the above
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3. Assume that a computer system uses m bits for logical address and n bits for physical address. The logical address space size is 2m bytes, and the page size is 2n bytes. The number of bits required to represent the page number and offset are
(A) (n – m) bits, and n bits
(B) n bits, and m bits
(C) (m – n) bits, and n bits
(D) (m – n) bits, and m bits
(E) m bits, and n bits
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4. The wastage of memory within a partition or paging is called as
(A) External fragmentation
(B) Internal fragmentation
(C) Segmentation
(D) De-fragmentation
(E) Segmented with paging
Answer :-
5. Assume that a computer system uses a paging scheme. The page size 4KB. The size of the user process is 50000 bytes. What amount of memory will be wasted?
(A) 1632 Bytes
(B) 2048 bytes
(C) 3048 bytes
(D) 3248 Bytes
(E) 4092 Bytes
Answer :-
6. Assume that a computer system is using the two-level paging scheme. The size of the page is 4KB. Assume that the size of each entry in page tables is 4 bytes. The computer system used a 64-bit logical address and a 64-bit physical address. The first-level page table has 232 entries, and each second-level page table also has 220 entries. The system uses a single MMU register for the first-level page table entry. What is the size of the total memory consumed by the first-level and second-level page tables?
(A) 16GB and 4MB
(B) 4MB and 15GB
(C) 8GB and 8GB
(D) 16GB and 4GB
(E) 16GB and 16GB
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7. Assume that a computer system follows “fixed variable multiple partitions” memory allocation method. The memory is partitioned as follows (in order):
| Block Number | Block Siza |
| 1 | 200KB |
| 2 | 350KB |
| 3 | 100KB |
| 4 | 400KB |
| 5 | 375KB |
The Best-fit memory management algorithm places the following processes of size 218KB, 410KB, 115KB, 345KB, and 100KB (in order). What is the amount of internal and external fragmentations?
(A) 600KB and 47KB
(B) 47KB and 400KB
(C) 47KB and 200KB
(D) 47KB and 600KB
(E) 200KB and 400KB
Answer :-
8. Choose the correct statement.
(A) Compaction is possible only for variable-sized memory partitions
(B) Compaction is primarily used to reduce external fragmentation
(C) Compaction is only possible if dynamic memory allocation is available
(D) Compaction cannot be executed while I/O is in progress
(E) All of the above
Answer :-
9. The Segment-Table Base Register (STBR) is used to hold
(A) the size of each segment in memory
(B) the base address of the segment table
(C) the end address of each segment
(D) the physical address of the CPU registers
(E) the allocation status of system memory
Answer :-
10. The Page-Table Length Register (PTLR) is used in the paging scheme to
(A) hold the number of pages currently in use
(B) hold the base address of the page table
(C) manage the cache for page table entries
(D) store the addresses of the page table entries
(E) indicate the length of the page table in memory
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