NPTEL Digital Circuits Week 8 Assignment Answers 2024
1. How many comparators are required for 4-bit flash type ADC?
A) 7
B) 15
C) 31
D) 63
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2.
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3. What is the resolution of an 8-bit R-2R ladder DAC? Assume the reference voltage (Vret) to be 5 V.
A) 3.91 mv
B) 7.8125 mv
C) 15.625 mv
D) 19.53 mv
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4.
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5.
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6. Size of the priority encoder required for 4-bit flash ADC?
A) 16×4
B) 4×2
C) 8×3
D) 32×5
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7. What is the primary advantage of using a Mealy FSM over a Moore FSM?
A) Simplicity in design.
B) Faster response to input changes.
C) Output stability during state transitions.
D) Reduced state complexity.
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8.
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9. Which of the following statement is TRUE?
A) Binary weighted DAC has lower conversion speed than R-2R ladder DAC
B) R-2R ladder DAC has lower conversion speed than binary weighted DAC
C) R-2R ladder DAC require high precision resistors.
D) Binary weighted DAC requires only two resistor values.
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10. A 4-bit R-2R ladder DAC produces output voltage of -5V for the input (B, B2 B, Bo) = 1001. What is the
reference voltage (Vret)?
A) 13.33
B) 8.89
C) 10
D) 15
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11.
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12. Which of the following element is essential in sample and hold circuit?
A) Resistor
B) Inductor
C) Capacitor
D) Transformer
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13. Which of the following steps is not present in the ADC conversion process?
A) Sampling and holding
B) Quantization
C) Encoding
D) Decoding
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14. What is the condition to avoid aliasing effect during sampling an analog signal?
A) Sampling frequency is at least twice of the maximum input signal frequency.
B) Sampling frequency is at most twice of the maximum input signal frequency.
C) Sampling frequency is at least 3 times of the maximum input signal frequency.
D) Sampling frequency is at most 1.5 times of the maximum input signal frequency.
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15. Which of the following ADC is more expensive to build?
A) Dual slope ADC
B) Successive approximation ADC
C) Flash type ADC
D) None of the above
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